URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 181

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Rev	Log message	Author	Age	Path
181	Simulation reports added.	simont	7708d 19h	/8051/tags/rel_12/rtl/verilog/
179	add /* synopsys xx_case */ to case statments.	simont	7708d 20h	/8051/tags/rel_12/rtl/verilog/
178	x replaced with 0.	simont	7708d 22h	/8051/tags/rel_12/rtl/verilog/
177	Fix bug in case of writing and reading from same address.	simont	7720d 01h	/8051/tags/rel_12/rtl/verilog/
175	initial inport.	simont	7720d 03h	/8051/tags/rel_12/rtl/verilog/
174	ram modules added.	simont	7720d 03h	/8051/tags/rel_12/rtl/verilog/
173	simualtion `ifdef added	simont	7720d 03h	/8051/tags/rel_12/rtl/verilog/
172	BIST signals added.	simont	7723d 02h	/8051/tags/rel_12/rtl/verilog/
171	fix bug in DA operation.	simont	7731d 00h	/8051/tags/rel_12/rtl/verilog/
158	fix bug.	simont	7735d 05h	/8051/tags/rel_12/rtl/verilog/
153	`ifdef added.	simont	7736d 23h	/8051/tags/rel_12/rtl/verilog/
152	sub_result output added.	simont	7736d 23h	/8051/tags/rel_12/rtl/verilog/
151	remove pc_r register.	simont	7736d 23h	/8051/tags/rel_12/rtl/verilog/
150	fix some bugs.	simont	7736d 23h	/8051/tags/rel_12/rtl/verilog/
149	pipelined acces to axternal instruction interface added.	simont	7736d 23h	/8051/tags/rel_12/rtl/verilog/
148	include "8051_defines" added.	simont	7737d 00h	/8051/tags/rel_12/rtl/verilog/
146	fix bug in movc intruction.	simont	7759d 00h	/8051/tags/rel_12/rtl/verilog/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7764d 04h	/8051/tags/rel_12/rtl/verilog/
144	chsnge comp.des to des1	simont	7764d 04h	/8051/tags/rel_12/rtl/verilog/
143	add wire sub_result, conect it to des_acc and des1.	simont	7764d 04h	/8051/tags/rel_12/rtl/verilog/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 181

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