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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 28

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Rev Log message Author Age Path
28 remove syn signal simont 8021d 12h /8051/tags/rel_12/rtl/verilog/
27 fix some bugs simont 8021d 12h /8051/tags/rel_12/rtl/verilog/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8021d 14h /8051/tags/rel_12/rtl/verilog/
25 divider and multiplier pass test markom 8022d 09h /8051/tags/rel_12/rtl/verilog/
23 mul & div use 4 clocks simont 8023d 04h /8051/tags/rel_12/rtl/verilog/
22 fix some bugs simont 8023d 04h /8051/tags/rel_12/rtl/verilog/
21 mul bug fixed markom 8023d 09h /8051/tags/rel_12/rtl/verilog/
20 multiplier and divider changed so they complete in 4 cycles markom 8023d 12h /8051/tags/rel_12/rtl/verilog/
19 combinatorial loop removed simont 8024d 04h /8051/tags/rel_12/rtl/verilog/
17 fix some bugs simont 8027d 09h /8051/tags/rel_12/rtl/verilog/
16 inputs ram and op2 removed simont 8027d 10h /8051/tags/rel_12/rtl/verilog/
15 commbinatorial loop removed simont 8027d 10h /8051/tags/rel_12/rtl/verilog/
13 some bug fix simont 8028d 08h /8051/tags/rel_12/rtl/verilog/
12 des1_r in alu port list simont 8028d 08h /8051/tags/rel_12/rtl/verilog/
11 des2_r removed simont 8028d 08h /8051/tags/rel_12/rtl/verilog/
10 % replaced with ^ in uart; some minor improvements markom 8028d 14h /8051/tags/rel_12/rtl/verilog/
9 removed unused compare states markom 8030d 07h /8051/tags/rel_12/rtl/verilog/
8 some IDS optimizations markom 8030d 07h /8051/tags/rel_12/rtl/verilog/
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 8030d 08h /8051/tags/rel_12/rtl/verilog/
6 psw combinatorial loop removed markom 8030d 10h /8051/tags/rel_12/rtl/verilog/

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