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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 31

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Rev Log message Author Age Path
31 fix some bugs simont 8053d 23h /8051/tags/rel_12/rtl/verilog/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 8057d 05h /8051/tags/rel_12/rtl/verilog/
29 fix some bugs simont 8057d 06h /8051/tags/rel_12/rtl/verilog/
28 remove syn signal simont 8057d 06h /8051/tags/rel_12/rtl/verilog/
27 fix some bugs simont 8057d 06h /8051/tags/rel_12/rtl/verilog/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8057d 08h /8051/tags/rel_12/rtl/verilog/
25 divider and multiplier pass test markom 8058d 02h /8051/tags/rel_12/rtl/verilog/
23 mul & div use 4 clocks simont 8058d 22h /8051/tags/rel_12/rtl/verilog/
22 fix some bugs simont 8058d 22h /8051/tags/rel_12/rtl/verilog/
21 mul bug fixed markom 8059d 03h /8051/tags/rel_12/rtl/verilog/
20 multiplier and divider changed so they complete in 4 cycles markom 8059d 05h /8051/tags/rel_12/rtl/verilog/
19 combinatorial loop removed simont 8059d 22h /8051/tags/rel_12/rtl/verilog/
17 fix some bugs simont 8063d 03h /8051/tags/rel_12/rtl/verilog/
16 inputs ram and op2 removed simont 8063d 03h /8051/tags/rel_12/rtl/verilog/
15 commbinatorial loop removed simont 8063d 03h /8051/tags/rel_12/rtl/verilog/
13 some bug fix simont 8064d 02h /8051/tags/rel_12/rtl/verilog/
12 des1_r in alu port list simont 8064d 02h /8051/tags/rel_12/rtl/verilog/
11 des2_r removed simont 8064d 02h /8051/tags/rel_12/rtl/verilog/
10 % replaced with ^ in uart; some minor improvements markom 8064d 08h /8051/tags/rel_12/rtl/verilog/
9 removed unused compare states markom 8066d 00h /8051/tags/rel_12/rtl/verilog/

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