URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 38

Rev	Log message	Author	Age	Path
38	fix some bugs	simont	7987d 21h	/8051/tags/rel_12/rtl/verilog/
37	added signals ack, stb and cyc	simont	7987d 21h	/8051/tags/rel_12/rtl/verilog/
36	fix bugs in mode 0	simont	7987d 21h	/8051/tags/rel_12/rtl/verilog/
32	overflow repaired	simont	7989d 02h	/8051/tags/rel_12/rtl/verilog/
31	fix some bugs	simont	7995d 18h	/8051/tags/rel_12/rtl/verilog/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7999d 00h	/8051/tags/rel_12/rtl/verilog/
29	fix some bugs	simont	7999d 01h	/8051/tags/rel_12/rtl/verilog/
28	remove syn signal	simont	7999d 01h	/8051/tags/rel_12/rtl/verilog/
27	fix some bugs	simont	7999d 01h	/8051/tags/rel_12/rtl/verilog/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7999d 03h	/8051/tags/rel_12/rtl/verilog/
25	divider and multiplier pass test	markom	7999d 22h	/8051/tags/rel_12/rtl/verilog/
23	mul & div use 4 clocks	simont	8000d 17h	/8051/tags/rel_12/rtl/verilog/
22	fix some bugs	simont	8000d 17h	/8051/tags/rel_12/rtl/verilog/
21	mul bug fixed	markom	8000d 22h	/8051/tags/rel_12/rtl/verilog/
20	multiplier and divider changed so they complete in 4 cycles	markom	8001d 01h	/8051/tags/rel_12/rtl/verilog/
19	combinatorial loop removed	simont	8001d 17h	/8051/tags/rel_12/rtl/verilog/
17	fix some bugs	simont	8004d 23h	/8051/tags/rel_12/rtl/verilog/
16	inputs ram and op2 removed	simont	8004d 23h	/8051/tags/rel_12/rtl/verilog/
15	commbinatorial loop removed	simont	8004d 23h	/8051/tags/rel_12/rtl/verilog/
13	some bug fix	simont	8005d 21h	/8051/tags/rel_12/rtl/verilog/