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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 41

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Rev Log message Author Age Path
41 remove unused files simont 7983d 04h /8051/tags/rel_12/rtl/verilog/
40 added sigals for interacting with external ram simont 8003d 06h /8051/tags/rel_12/rtl/verilog/
38 fix some bugs simont 8010d 04h /8051/tags/rel_12/rtl/verilog/
37 added signals ack, stb and cyc simont 8010d 04h /8051/tags/rel_12/rtl/verilog/
36 fix bugs in mode 0 simont 8010d 04h /8051/tags/rel_12/rtl/verilog/
32 overflow repaired simont 8011d 09h /8051/tags/rel_12/rtl/verilog/
31 fix some bugs simont 8018d 01h /8051/tags/rel_12/rtl/verilog/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 8021d 07h /8051/tags/rel_12/rtl/verilog/
29 fix some bugs simont 8021d 08h /8051/tags/rel_12/rtl/verilog/
28 remove syn signal simont 8021d 08h /8051/tags/rel_12/rtl/verilog/
27 fix some bugs simont 8021d 09h /8051/tags/rel_12/rtl/verilog/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8021d 10h /8051/tags/rel_12/rtl/verilog/
25 divider and multiplier pass test markom 8022d 05h /8051/tags/rel_12/rtl/verilog/
23 mul & div use 4 clocks simont 8023d 00h /8051/tags/rel_12/rtl/verilog/
22 fix some bugs simont 8023d 00h /8051/tags/rel_12/rtl/verilog/
21 mul bug fixed markom 8023d 06h /8051/tags/rel_12/rtl/verilog/
20 multiplier and divider changed so they complete in 4 cycles markom 8023d 08h /8051/tags/rel_12/rtl/verilog/
19 combinatorial loop removed simont 8024d 00h /8051/tags/rel_12/rtl/verilog/
17 fix some bugs simont 8027d 06h /8051/tags/rel_12/rtl/verilog/
16 inputs ram and op2 removed simont 8027d 06h /8051/tags/rel_12/rtl/verilog/

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