URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 54

Rev	Log message	Author	Age	Path
54	cahnge interface to instruction rom	simont	8001d 19h	/8051/tags/rel_12/rtl/verilog/
47	remove unused files	simont	8018d 20h	/8051/tags/rel_12/rtl/verilog/
46	prepared header	simont	8018d 20h	/8051/tags/rel_12/rtl/verilog/
45	prepared header	simont	8018d 21h	/8051/tags/rel_12/rtl/verilog/
44	prepared header	simont	8018d 21h	/8051/tags/rel_12/rtl/verilog/
41	remove unused files	simont	8018d 23h	/8051/tags/rel_12/rtl/verilog/
40	added sigals for interacting with external ram	simont	8039d 00h	/8051/tags/rel_12/rtl/verilog/
38	fix some bugs	simont	8045d 23h	/8051/tags/rel_12/rtl/verilog/
37	added signals ack, stb and cyc	simont	8045d 23h	/8051/tags/rel_12/rtl/verilog/
36	fix bugs in mode 0	simont	8045d 23h	/8051/tags/rel_12/rtl/verilog/
32	overflow repaired	simont	8047d 03h	/8051/tags/rel_12/rtl/verilog/
31	fix some bugs	simont	8053d 20h	/8051/tags/rel_12/rtl/verilog/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	8057d 02h	/8051/tags/rel_12/rtl/verilog/
29	fix some bugs	simont	8057d 03h	/8051/tags/rel_12/rtl/verilog/
28	remove syn signal	simont	8057d 03h	/8051/tags/rel_12/rtl/verilog/
27	fix some bugs	simont	8057d 03h	/8051/tags/rel_12/rtl/verilog/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8057d 05h	/8051/tags/rel_12/rtl/verilog/
25	divider and multiplier pass test	markom	8057d 23h	/8051/tags/rel_12/rtl/verilog/
23	mul & div use 4 clocks	simont	8058d 19h	/8051/tags/rel_12/rtl/verilog/
22	fix some bugs	simont	8058d 19h	/8051/tags/rel_12/rtl/verilog/