URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 76

Rev	Log message	Author	Age	Path
76	add module oc8051_sfr, 256 bytes internal ram	simont	7919d 12h	/8051/tags/rel_12/rtl/verilog/
75	initial import	simont	7919d 12h	/8051/tags/rel_12/rtl/verilog/
73	initial import	simont	7927d 13h	/8051/tags/rel_12/rtl/verilog/
72	fix bug in interface to external data ram	simont	7927d 15h	/8051/tags/rel_12/rtl/verilog/
67	add parameters for instruction cache	simont	7931d 16h	/8051/tags/rel_12/rtl/verilog/
62	fix bugs in instruction interface	simont	7932d 13h	/8051/tags/rel_12/rtl/verilog/
54	cahnge interface to instruction rom	simont	7938d 11h	/8051/tags/rel_12/rtl/verilog/
47	remove unused files	simont	7955d 12h	/8051/tags/rel_12/rtl/verilog/
46	prepared header	simont	7955d 12h	/8051/tags/rel_12/rtl/verilog/
45	prepared header	simont	7955d 13h	/8051/tags/rel_12/rtl/verilog/
44	prepared header	simont	7955d 13h	/8051/tags/rel_12/rtl/verilog/
41	remove unused files	simont	7955d 14h	/8051/tags/rel_12/rtl/verilog/
40	added sigals for interacting with external ram	simont	7975d 16h	/8051/tags/rel_12/rtl/verilog/
38	fix some bugs	simont	7982d 15h	/8051/tags/rel_12/rtl/verilog/
37	added signals ack, stb and cyc	simont	7982d 15h	/8051/tags/rel_12/rtl/verilog/
36	fix bugs in mode 0	simont	7982d 15h	/8051/tags/rel_12/rtl/verilog/
32	overflow repaired	simont	7983d 19h	/8051/tags/rel_12/rtl/verilog/
31	fix some bugs	simont	7990d 11h	/8051/tags/rel_12/rtl/verilog/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7993d 18h	/8051/tags/rel_12/rtl/verilog/
29	fix some bugs	simont	7993d 19h	/8051/tags/rel_12/rtl/verilog/