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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 78

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Rev Log message Author Age Path
78 alu with registered outputs simont 7915d 22h /8051/tags/rel_12/rtl/verilog/
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 7924d 19h /8051/tags/rel_12/rtl/verilog/
76 add module oc8051_sfr, 256 bytes internal ram simont 7924d 19h /8051/tags/rel_12/rtl/verilog/
75 initial import simont 7924d 19h /8051/tags/rel_12/rtl/verilog/
73 initial import simont 7932d 19h /8051/tags/rel_12/rtl/verilog/
72 fix bug in interface to external data ram simont 7932d 21h /8051/tags/rel_12/rtl/verilog/
67 add parameters for instruction cache simont 7936d 23h /8051/tags/rel_12/rtl/verilog/
62 fix bugs in instruction interface simont 7937d 19h /8051/tags/rel_12/rtl/verilog/
54 cahnge interface to instruction rom simont 7943d 17h /8051/tags/rel_12/rtl/verilog/
47 remove unused files simont 7960d 19h /8051/tags/rel_12/rtl/verilog/
46 prepared header simont 7960d 19h /8051/tags/rel_12/rtl/verilog/
45 prepared header simont 7960d 19h /8051/tags/rel_12/rtl/verilog/
44 prepared header simont 7960d 19h /8051/tags/rel_12/rtl/verilog/
41 remove unused files simont 7960d 21h /8051/tags/rel_12/rtl/verilog/
40 added sigals for interacting with external ram simont 7980d 23h /8051/tags/rel_12/rtl/verilog/
38 fix some bugs simont 7987d 21h /8051/tags/rel_12/rtl/verilog/
37 added signals ack, stb and cyc simont 7987d 21h /8051/tags/rel_12/rtl/verilog/
36 fix bugs in mode 0 simont 7987d 21h /8051/tags/rel_12/rtl/verilog/
32 overflow repaired simont 7989d 01h /8051/tags/rel_12/rtl/verilog/
31 fix some bugs simont 7995d 18h /8051/tags/rel_12/rtl/verilog/

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