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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 87

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Rev Log message Author Age Path
87 add include oc8051_defines.v simont 7877d 21h /8051/tags/rel_12/rtl/verilog/
82 replace some modules simont 7885d 21h /8051/tags/rel_12/rtl/verilog/
81 initial import simont 7885d 21h /8051/tags/rel_12/rtl/verilog/
80 removing unused modules simont 7885d 21h /8051/tags/rel_12/rtl/verilog/
78 alu with registered outputs simont 7945d 21h /8051/tags/rel_12/rtl/verilog/
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 7954d 18h /8051/tags/rel_12/rtl/verilog/
76 add module oc8051_sfr, 256 bytes internal ram simont 7954d 18h /8051/tags/rel_12/rtl/verilog/
75 initial import simont 7954d 18h /8051/tags/rel_12/rtl/verilog/
73 initial import simont 7962d 18h /8051/tags/rel_12/rtl/verilog/
72 fix bug in interface to external data ram simont 7962d 20h /8051/tags/rel_12/rtl/verilog/
67 add parameters for instruction cache simont 7966d 22h /8051/tags/rel_12/rtl/verilog/
62 fix bugs in instruction interface simont 7967d 18h /8051/tags/rel_12/rtl/verilog/
54 cahnge interface to instruction rom simont 7973d 16h /8051/tags/rel_12/rtl/verilog/
47 remove unused files simont 7990d 18h /8051/tags/rel_12/rtl/verilog/
46 prepared header simont 7990d 18h /8051/tags/rel_12/rtl/verilog/
45 prepared header simont 7990d 18h /8051/tags/rel_12/rtl/verilog/
44 prepared header simont 7990d 18h /8051/tags/rel_12/rtl/verilog/
41 remove unused files simont 7990d 20h /8051/tags/rel_12/rtl/verilog/
40 added sigals for interacting with external ram simont 8010d 22h /8051/tags/rel_12/rtl/verilog/
38 fix some bugs simont 8017d 20h /8051/tags/rel_12/rtl/verilog/

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