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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 94

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Rev Log message Author Age Path
94 fix bug. simont 7799d 10h /8051/tags/rel_12/rtl/verilog/
93 OC8051_XILINX_RAM added simont 7799d 10h /8051/tags/rel_12/rtl/verilog/
92 initial inport simont 7799d 10h /8051/tags/rel_12/rtl/verilog/
90 change module name. simont 7804d 04h /8051/tags/rel_12/rtl/verilog/
89 Replaced oc8051_ram by generic_dpram. rherveille 7865d 07h /8051/tags/rel_12/rtl/verilog/
88 fix bugs simont 7870d 07h /8051/tags/rel_12/rtl/verilog/
87 add include oc8051_defines.v simont 7870d 08h /8051/tags/rel_12/rtl/verilog/
82 replace some modules simont 7878d 07h /8051/tags/rel_12/rtl/verilog/
81 initial import simont 7878d 07h /8051/tags/rel_12/rtl/verilog/
80 removing unused modules simont 7878d 07h /8051/tags/rel_12/rtl/verilog/
78 alu with registered outputs simont 7938d 07h /8051/tags/rel_12/rtl/verilog/
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 7947d 04h /8051/tags/rel_12/rtl/verilog/
76 add module oc8051_sfr, 256 bytes internal ram simont 7947d 04h /8051/tags/rel_12/rtl/verilog/
75 initial import simont 7947d 04h /8051/tags/rel_12/rtl/verilog/
73 initial import simont 7955d 05h /8051/tags/rel_12/rtl/verilog/
72 fix bug in interface to external data ram simont 7955d 07h /8051/tags/rel_12/rtl/verilog/
67 add parameters for instruction cache simont 7959d 08h /8051/tags/rel_12/rtl/verilog/
62 fix bugs in instruction interface simont 7960d 05h /8051/tags/rel_12/rtl/verilog/
54 cahnge interface to instruction rom simont 7966d 03h /8051/tags/rel_12/rtl/verilog/
47 remove unused files simont 7983d 04h /8051/tags/rel_12/rtl/verilog/

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