URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [sim/] - Rev 106

Rev	Log message	Author	Age	Path
106	generic_dpram used	simont	7771d 15h	/8051/tags/rel_12/sim/
101	initial inport	simont	7771d 20h	/8051/tags/rel_12/sim/
100	use \	simont	7771d 20h	/8051/tags/rel_12/sim/
99	change directory structure	simont	7771d 20h	/8051/tags/rel_12/sim/
98	move to rtl/verilog	simont	7771d 20h	/8051/tags/rel_12/sim/
85	prepare bugs	simont	7842d 18h	/8051/tags/rel_12/sim/
83	replace some modules	simont	7850d 17h	/8051/tags/rel_12/sim/
82	replace some modules	simont	7850d 17h	/8051/tags/rel_12/sim/
69	add parameters	simont	7931d 18h	/8051/tags/rel_12/sim/
66	added xrom_test	simont	7932d 14h	/8051/tags/rel_12/sim/
65	add oc8051_icache and oc8051_cache_ram	simont	7932d 14h	/8051/tags/rel_12/sim/
64	signal es_int=1'b0	simont	7932d 14h	/8051/tags/rel_12/sim/
63	initial import	simont	7932d 14h	/8051/tags/rel_12/sim/
58	add external rom testing	simont	7938d 12h	/8051/tags/rel_12/sim/
57	add module oc8051_xrom	simont	7938d 12h	/8051/tags/rel_12/sim/
56	initial CVS input	simont	7938d 12h	/8051/tags/rel_12/sim/
55	added parameter DELAY	simont	7938d 13h	/8051/tags/rel_12/sim/
46	prepared header	simont	7955d 14h	/8051/tags/rel_12/sim/
43	remove unused files	simont	7955d 16h	/8051/tags/rel_12/sim/
42	* empty log message *	simont	7955d 16h	/8051/tags/rel_12/sim/