URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [sim/] - Rev 66

Rev	Log message	Author	Age	Path
66	added xrom_test	simont	7920d 06h	/8051/tags/rel_12/sim/
65	add oc8051_icache and oc8051_cache_ram	simont	7920d 06h	/8051/tags/rel_12/sim/
64	signal es_int=1'b0	simont	7920d 06h	/8051/tags/rel_12/sim/
63	initial import	simont	7920d 06h	/8051/tags/rel_12/sim/
58	add external rom testing	simont	7926d 04h	/8051/tags/rel_12/sim/
57	add module oc8051_xrom	simont	7926d 04h	/8051/tags/rel_12/sim/
56	initial CVS input	simont	7926d 04h	/8051/tags/rel_12/sim/
55	added parameter DELAY	simont	7926d 04h	/8051/tags/rel_12/sim/
46	prepared header	simont	7943d 06h	/8051/tags/rel_12/sim/
43	remove unused files	simont	7943d 07h	/8051/tags/rel_12/sim/
42	* empty log message *	simont	7943d 07h	/8051/tags/rel_12/sim/
41	remove unused files	simont	7943d 08h	/8051/tags/rel_12/sim/
37	added signals ack, stb and cyc	simont	7970d 08h	/8051/tags/rel_12/sim/
19	combinatorial loop removed	simont	7984d 04h	/8051/tags/rel_12/sim/
18	rst signal added	simont	7987d 09h	/8051/tags/rel_12/sim/
4	Code repaired to satisfy the linter; testbech fails	markom	7990d 12h	/8051/tags/rel_12/sim/
2	Initial CVS import	simont	8006d 10h	/8051/tags/rel_12/sim/