URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] - Rev 131

Rev	Log message	Author	Age	Path
131	prepare programs for new timing.	simont	7736d 07h	/8051/tags/rel_19/
130	prepared programs for new timing.	simont	7736d 07h	/8051/tags/rel_19/
129	updated...	simont	7736d 07h	/8051/tags/rel_19/
128	chance idat_ir to 24 bit wide	simont	7745d 14h	/8051/tags/rel_19/
127	fix bug (cyc_o and stb_o)	simont	7745d 14h	/8051/tags/rel_19/
126	define OC8051_XILINX_RAMB added	simont	7745d 14h	/8051/tags/rel_19/
125	update, add prescaler, rclk, tclk.	simont	7745d 14h	/8051/tags/rel_19/
124	add support for external rom from xilinx ramb4	simont	7745d 14h	/8051/tags/rel_19/
123	fiz bug iv pcs operation.	simont	7747d 10h	/8051/tags/rel_19/
122	deifne OC8051_ROM added	simont	7750d 14h	/8051/tags/rel_19/
121	Change pc add value from 23'h to 16'h	simont	7750d 14h	/8051/tags/rel_19/
120	defines for pherypherals added	simont	7751d 12h	/8051/tags/rel_19/
119	remove signal sbuf_txd [12:11]	simont	7751d 15h	/8051/tags/rel_19/
118	change wr_sft to 2 bit wire.	simont	7752d 08h	/8051/tags/rel_19/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7752d 08h	/8051/tags/rel_19/
116	change sfr's interface.	simont	7754d 09h	/8051/tags/rel_19/
115	change uart to meet timing.	simont	7754d 11h	/8051/tags/rel_19/
114	remove t2mod register	simont	7757d 14h	/8051/tags/rel_19/
113	signal prsc_ow added.	simont	7757d 14h	/8051/tags/rel_19/
112	change timers to meet timing specifications (add divider with 12)	simont	7757d 14h	/8051/tags/rel_19/