URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] - Rev 137

Rev	Log message	Author	Age	Path
137	change to fit xrom.	simont	7740d 05h	/8051/tags/rel_19/
136	registering outputs.	simont	7740d 05h	/8051/tags/rel_19/
135	prepared start of receiving if ren is not active.	simont	7746d 04h	/8051/tags/rel_19/
134	fix bug in case execution of two data dependent instructions.	simont	7746d 04h	/8051/tags/rel_19/
133	fix bug in substraction.	simont	7746d 07h	/8051/tags/rel_19/
132	change branch instruction execution (reduse needed clock periods).	simont	7749d 22h	/8051/tags/rel_19/
131	prepare programs for new timing.	simont	7749d 22h	/8051/tags/rel_19/
130	prepared programs for new timing.	simont	7749d 22h	/8051/tags/rel_19/
129	updated...	simont	7749d 22h	/8051/tags/rel_19/
128	chance idat_ir to 24 bit wide	simont	7759d 06h	/8051/tags/rel_19/
127	fix bug (cyc_o and stb_o)	simont	7759d 06h	/8051/tags/rel_19/
126	define OC8051_XILINX_RAMB added	simont	7759d 06h	/8051/tags/rel_19/
125	update, add prescaler, rclk, tclk.	simont	7759d 06h	/8051/tags/rel_19/
124	add support for external rom from xilinx ramb4	simont	7759d 06h	/8051/tags/rel_19/
123	fiz bug iv pcs operation.	simont	7761d 01h	/8051/tags/rel_19/
122	deifne OC8051_ROM added	simont	7764d 06h	/8051/tags/rel_19/
121	Change pc add value from 23'h to 16'h	simont	7764d 06h	/8051/tags/rel_19/
120	defines for pherypherals added	simont	7765d 03h	/8051/tags/rel_19/
119	remove signal sbuf_txd [12:11]	simont	7765d 07h	/8051/tags/rel_19/
118	change wr_sft to 2 bit wire.	simont	7765d 23h	/8051/tags/rel_19/