URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] - Rev 151

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Rev	Log message	Author	Age	Path
151	remove pc_r register.	simont	7705d 13h	/8051/tags/rel_19/
150	fix some bugs.	simont	7705d 13h	/8051/tags/rel_19/
149	pipelined acces to axternal instruction interface added.	simont	7705d 13h	/8051/tags/rel_19/
148	include "8051_defines" added.	simont	7705d 13h	/8051/tags/rel_19/
146	fix bug in movc intruction.	simont	7727d 14h	/8051/tags/rel_19/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7732d 18h	/8051/tags/rel_19/
144	chsnge comp.des to des1	simont	7732d 18h	/8051/tags/rel_19/
143	add wire sub_result, conect it to des_acc and des1.	simont	7732d 18h	/8051/tags/rel_19/
142	optimize state machine.	simont	7733d 19h	/8051/tags/rel_19/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7733d 21h	/8051/tags/rel_19/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7733d 21h	/8051/tags/rel_19/
139	add aditional alu destination to solve critical path.	simont	7734d 15h	/8051/tags/rel_19/
138	Change buffering to save one clock per instruction.	simont	7734d 15h	/8051/tags/rel_19/
137	change to fit xrom.	simont	7734d 20h	/8051/tags/rel_19/
136	registering outputs.	simont	7734d 20h	/8051/tags/rel_19/
135	prepared start of receiving if ren is not active.	simont	7740d 19h	/8051/tags/rel_19/
134	fix bug in case execution of two data dependent instructions.	simont	7740d 19h	/8051/tags/rel_19/
133	fix bug in substraction.	simont	7740d 22h	/8051/tags/rel_19/
132	change branch instruction execution (reduse needed clock periods).	simont	7744d 13h	/8051/tags/rel_19/
131	prepare programs for new timing.	simont	7744d 13h	/8051/tags/rel_19/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] - Rev 151

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