OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] - Rev 177

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
177 Fix bug in case of writing and reading from same address. simont 7667d 11h /8051/tags/rel_19/
176 ram modules added. simont 7667d 13h /8051/tags/rel_19/
175 initial inport. simont 7667d 13h /8051/tags/rel_19/
174 ram modules added. simont 7667d 13h /8051/tags/rel_19/
173 simualtion `ifdef added simont 7667d 13h /8051/tags/rel_19/
172 BIST signals added. simont 7670d 12h /8051/tags/rel_19/
171 fix bug in DA operation. simont 7678d 10h /8051/tags/rel_19/
170 removing unused files. simont 7678d 10h /8051/tags/rel_19/
169 remove unused files. simont 7678d 10h /8051/tags/rel_19/
168 modify program list. simont 7678d 11h /8051/tags/rel_19/
167 add readmem for ea. simont 7681d 16h /8051/tags/rel_19/
166 Change test monitor from ports to external data memory. simont 7682d 09h /8051/tags/rel_19/
165 remove dumpvars. simont 7682d 14h /8051/tags/rel_19/
164 initial inport. simont 7682d 14h /8051/tags/rel_19/
163 initial inport simont 7682d 14h /8051/tags/rel_19/
162 initial inport. simont 7682d 15h /8051/tags/rel_19/
161 fix file names. simont 7682d 15h /8051/tags/rel_19/
160 initial inport. simont 7682d 15h /8051/tags/rel_19/
159 initial inport. simont 7682d 15h /8051/tags/rel_19/
158 fix bug. simont 7682d 15h /8051/tags/rel_19/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.