URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] [bench/] - Rev 120

Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7778d 04h	/8051/tags/rel_19/bench/
111	Remove instruction cache and wb_interface	simont	7784d 22h	/8051/tags/rel_19/bench/
103	rename signals	simont	7786d 02h	/8051/tags/rel_19/bench/
97	initial inport	simont	7786d 05h	/8051/tags/rel_19/bench/
96	initial import	simont	7786d 05h	/8051/tags/rel_19/bench/
84	remove wb_bus_mon	simont	7865d 02h	/8051/tags/rel_19/bench/
74	add module oc8051_wb_iinterface	simont	7942d 00h	/8051/tags/rel_19/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7946d 03h	/8051/tags/rel_19/bench/
59	add external rom	simont	7952d 22h	/8051/tags/rel_19/bench/
46	prepared header	simont	7969d 23h	/8051/tags/rel_19/bench/
37	added signals ack, stb and cyc	simont	7997d 02h	/8051/tags/rel_19/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	8017d 06h	/8051/tags/rel_19/bench/
2	Initial CVS import	simont	8033d 03h	/8051/tags/rel_19/bench/