URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] [bench/] - Rev 129

Rev	Log message	Author	Age	Path
129	updated...	simont	7732d 13h	/8051/tags/rel_19/bench/
125	update, add prescaler, rclk, tclk.	simont	7741d 20h	/8051/tags/rel_19/bench/
124	add support for external rom from xilinx ramb4	simont	7741d 20h	/8051/tags/rel_19/bench/
120	defines for pherypherals added	simont	7747d 17h	/8051/tags/rel_19/bench/
111	Remove instruction cache and wb_interface	simont	7754d 10h	/8051/tags/rel_19/bench/
103	rename signals	simont	7755d 15h	/8051/tags/rel_19/bench/
97	initial inport	simont	7755d 18h	/8051/tags/rel_19/bench/
96	initial import	simont	7755d 18h	/8051/tags/rel_19/bench/
84	remove wb_bus_mon	simont	7834d 15h	/8051/tags/rel_19/bench/
74	add module oc8051_wb_iinterface	simont	7911d 13h	/8051/tags/rel_19/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7915d 16h	/8051/tags/rel_19/bench/
59	add external rom	simont	7922d 11h	/8051/tags/rel_19/bench/
46	prepared header	simont	7939d 12h	/8051/tags/rel_19/bench/
37	added signals ack, stb and cyc	simont	7966d 15h	/8051/tags/rel_19/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	7986d 18h	/8051/tags/rel_19/bench/
2	Initial CVS import	simont	8002d 16h	/8051/tags/rel_19/bench/