URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 113

Rev	Log message	Author	Age	Path
113	signal prsc_ow added.	simont	7758d 06h	/8051/tags/rel_2/
112	change timers to meet timing specifications (add divider with 12)	simont	7758d 06h	/8051/tags/rel_2/
111	Remove instruction cache and wb_interface	simont	7758d 21h	/8051/tags/rel_2/
110	change adr_i and adr_o length.	simont	7758d 22h	/8051/tags/rel_2/
109	add `include "oc8051_defines.v"	simont	7758d 22h	/8051/tags/rel_2/
108	fix some bugs, use oc8051_cache_ram.	simont	7758d 22h	/8051/tags/rel_2/
107	Include instruction cache.	simont	7758d 22h	/8051/tags/rel_2/
106	generic_dpram used	simont	7760d 01h	/8051/tags/rel_2/
105	generic_dpram used	simont	7760d 01h	/8051/tags/rel_2/
104	use generic_dpram	simont	7760d 01h	/8051/tags/rel_2/
103	rename signals	simont	7760d 02h	/8051/tags/rel_2/
102	raname signals.	simont	7760d 02h	/8051/tags/rel_2/
101	initial inport	simont	7760d 05h	/8051/tags/rel_2/
100	use \	simont	7760d 05h	/8051/tags/rel_2/
99	change directory structure	simont	7760d 05h	/8051/tags/rel_2/
98	move to rtl/verilog	simont	7760d 05h	/8051/tags/rel_2/
97	initial inport	simont	7760d 05h	/8051/tags/rel_2/
96	initial import	simont	7760d 05h	/8051/tags/rel_2/
95	updating...	simont	7760d 05h	/8051/tags/rel_2/
94	fix bug.	simont	7760d 05h	/8051/tags/rel_2/