URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 124

Rev	Log message	Author	Age	Path
124	add support for external rom from xilinx ramb4	simont	7763d 04h	/8051/tags/rel_2/
123	fiz bug iv pcs operation.	simont	7764d 23h	/8051/tags/rel_2/
122	deifne OC8051_ROM added	simont	7768d 04h	/8051/tags/rel_2/
121	Change pc add value from 23'h to 16'h	simont	7768d 04h	/8051/tags/rel_2/
120	defines for pherypherals added	simont	7769d 01h	/8051/tags/rel_2/
119	remove signal sbuf_txd [12:11]	simont	7769d 05h	/8051/tags/rel_2/
118	change wr_sft to 2 bit wire.	simont	7769d 21h	/8051/tags/rel_2/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7769d 22h	/8051/tags/rel_2/
116	change sfr's interface.	simont	7771d 23h	/8051/tags/rel_2/
115	change uart to meet timing.	simont	7772d 00h	/8051/tags/rel_2/
114	remove t2mod register	simont	7775d 03h	/8051/tags/rel_2/
113	signal prsc_ow added.	simont	7775d 03h	/8051/tags/rel_2/
112	change timers to meet timing specifications (add divider with 12)	simont	7775d 03h	/8051/tags/rel_2/
111	Remove instruction cache and wb_interface	simont	7775d 18h	/8051/tags/rel_2/
110	change adr_i and adr_o length.	simont	7775d 18h	/8051/tags/rel_2/
109	add `include "oc8051_defines.v"	simont	7775d 18h	/8051/tags/rel_2/
108	fix some bugs, use oc8051_cache_ram.	simont	7775d 18h	/8051/tags/rel_2/
107	Include instruction cache.	simont	7775d 18h	/8051/tags/rel_2/
106	generic_dpram used	simont	7776d 21h	/8051/tags/rel_2/
105	generic_dpram used	simont	7776d 22h	/8051/tags/rel_2/