URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 136

Rev	Log message	Author	Age	Path
136	registering outputs.	simont	7726d 18h	/8051/tags/rel_2/
135	prepared start of receiving if ren is not active.	simont	7732d 17h	/8051/tags/rel_2/
134	fix bug in case execution of two data dependent instructions.	simont	7732d 17h	/8051/tags/rel_2/
133	fix bug in substraction.	simont	7732d 20h	/8051/tags/rel_2/
132	change branch instruction execution (reduse needed clock periods).	simont	7736d 12h	/8051/tags/rel_2/
131	prepare programs for new timing.	simont	7736d 12h	/8051/tags/rel_2/
130	prepared programs for new timing.	simont	7736d 12h	/8051/tags/rel_2/
129	updated...	simont	7736d 12h	/8051/tags/rel_2/
128	chance idat_ir to 24 bit wide	simont	7745d 19h	/8051/tags/rel_2/
127	fix bug (cyc_o and stb_o)	simont	7745d 19h	/8051/tags/rel_2/
126	define OC8051_XILINX_RAMB added	simont	7745d 19h	/8051/tags/rel_2/
125	update, add prescaler, rclk, tclk.	simont	7745d 19h	/8051/tags/rel_2/
124	add support for external rom from xilinx ramb4	simont	7745d 19h	/8051/tags/rel_2/
123	fiz bug iv pcs operation.	simont	7747d 14h	/8051/tags/rel_2/
122	deifne OC8051_ROM added	simont	7750d 19h	/8051/tags/rel_2/
121	Change pc add value from 23'h to 16'h	simont	7750d 19h	/8051/tags/rel_2/
120	defines for pherypherals added	simont	7751d 16h	/8051/tags/rel_2/
119	remove signal sbuf_txd [12:11]	simont	7751d 20h	/8051/tags/rel_2/
118	change wr_sft to 2 bit wire.	simont	7752d 12h	/8051/tags/rel_2/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7752d 13h	/8051/tags/rel_2/