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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 149

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Rev	Log message	Author	Age	Path
149	pipelined acces to axternal instruction interface added.	simont	7728d 20h	/8051/tags/rel_2/
148	include "8051_defines" added.	simont	7728d 21h	/8051/tags/rel_2/
146	fix bug in movc intruction.	simont	7750d 21h	/8051/tags/rel_2/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7756d 01h	/8051/tags/rel_2/
144	chsnge comp.des to des1	simont	7756d 01h	/8051/tags/rel_2/
143	add wire sub_result, conect it to des_acc and des1.	simont	7756d 01h	/8051/tags/rel_2/
142	optimize state machine.	simont	7757d 02h	/8051/tags/rel_2/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7757d 04h	/8051/tags/rel_2/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7757d 04h	/8051/tags/rel_2/
139	add aditional alu destination to solve critical path.	simont	7757d 22h	/8051/tags/rel_2/
138	Change buffering to save one clock per instruction.	simont	7757d 22h	/8051/tags/rel_2/
137	change to fit xrom.	simont	7758d 03h	/8051/tags/rel_2/
136	registering outputs.	simont	7758d 03h	/8051/tags/rel_2/
135	prepared start of receiving if ren is not active.	simont	7764d 02h	/8051/tags/rel_2/
134	fix bug in case execution of two data dependent instructions.	simont	7764d 02h	/8051/tags/rel_2/
133	fix bug in substraction.	simont	7764d 05h	/8051/tags/rel_2/
132	change branch instruction execution (reduse needed clock periods).	simont	7767d 20h	/8051/tags/rel_2/
131	prepare programs for new timing.	simont	7767d 20h	/8051/tags/rel_2/
130	prepared programs for new timing.	simont	7767d 20h	/8051/tags/rel_2/
129	updated...	simont	7767d 20h	/8051/tags/rel_2/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 149

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