OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 35

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
35 design docunemt simont 7978d 01h /8051/tags/rel_2/
34 specification docunemt simont 7978d 01h /8051/tags/rel_2/
33 fix some bugs simont 7978d 07h /8051/tags/rel_2/
32 overflow repaired simont 7978d 07h /8051/tags/rel_2/
31 fix some bugs simont 7984d 23h /8051/tags/rel_2/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 7988d 06h /8051/tags/rel_2/
29 fix some bugs simont 7988d 06h /8051/tags/rel_2/
28 remove syn signal simont 7988d 07h /8051/tags/rel_2/
27 fix some bugs simont 7988d 07h /8051/tags/rel_2/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7988d 09h /8051/tags/rel_2/
25 divider and multiplier pass test markom 7989d 03h /8051/tags/rel_2/
24 intensively tests all instructions markom 7989d 08h /8051/tags/rel_2/
23 mul & div use 4 clocks simont 7989d 22h /8051/tags/rel_2/
22 fix some bugs simont 7989d 23h /8051/tags/rel_2/
21 mul bug fixed markom 7990d 04h /8051/tags/rel_2/
20 multiplier and divider changed so they complete in 4 cycles markom 7990d 06h /8051/tags/rel_2/
19 combinatorial loop removed simont 7990d 23h /8051/tags/rel_2/
18 rst signal added simont 7994d 04h /8051/tags/rel_2/
17 fix some bugs simont 7994d 04h /8051/tags/rel_2/
16 inputs ram and op2 removed simont 7994d 04h /8051/tags/rel_2/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.