OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 78

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
78 alu with registered outputs simont 7912d 03h /8051/tags/rel_2/
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 7921d 00h /8051/tags/rel_2/
76 add module oc8051_sfr, 256 bytes internal ram simont 7921d 00h /8051/tags/rel_2/
75 initial import simont 7921d 00h /8051/tags/rel_2/
74 add module oc8051_wb_iinterface simont 7929d 01h /8051/tags/rel_2/
73 initial import simont 7929d 01h /8051/tags/rel_2/
72 fix bug in interface to external data ram simont 7929d 03h /8051/tags/rel_2/
71 add cache simont 7933d 02h /8051/tags/rel_2/
70 initial import simont 7933d 02h /8051/tags/rel_2/
69 add parameters simont 7933d 04h /8051/tags/rel_2/
68 add instruction cache and DELAY parameters for external ram, rom simont 7933d 04h /8051/tags/rel_2/
67 add parameters for instruction cache simont 7933d 04h /8051/tags/rel_2/
66 added xrom_test simont 7934d 00h /8051/tags/rel_2/
65 add oc8051_icache and oc8051_cache_ram simont 7934d 00h /8051/tags/rel_2/
64 signal es_int=1'b0 simont 7934d 01h /8051/tags/rel_2/
63 initial import simont 7934d 01h /8051/tags/rel_2/
62 fix bugs in instruction interface simont 7934d 01h /8051/tags/rel_2/
61 fix bug simont 7935d 03h /8051/tags/rel_2/
60 initial inport simont 7936d 04h /8051/tags/rel_2/
59 add external rom simont 7939d 23h /8051/tags/rel_2/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.