URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 83

Rev	Log message	Author	Age	Path
83	replace some modules	simont	7851d 22h	/8051/tags/rel_2/
82	replace some modules	simont	7851d 22h	/8051/tags/rel_2/
81	initial import	simont	7851d 22h	/8051/tags/rel_2/
80	removing unused modules	simont	7851d 22h	/8051/tags/rel_2/
79	initial import	simont	7851d 23h	/8051/tags/rel_2/
78	alu with registered outputs	simont	7911d 22h	/8051/tags/rel_2/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7920d 19h	/8051/tags/rel_2/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7920d 19h	/8051/tags/rel_2/
75	initial import	simont	7920d 19h	/8051/tags/rel_2/
74	add module oc8051_wb_iinterface	simont	7928d 20h	/8051/tags/rel_2/
73	initial import	simont	7928d 20h	/8051/tags/rel_2/
72	fix bug in interface to external data ram	simont	7928d 22h	/8051/tags/rel_2/
71	add cache	simont	7932d 21h	/8051/tags/rel_2/
70	initial import	simont	7932d 21h	/8051/tags/rel_2/
69	add parameters	simont	7932d 23h	/8051/tags/rel_2/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7932d 23h	/8051/tags/rel_2/
67	add parameters for instruction cache	simont	7932d 23h	/8051/tags/rel_2/
66	added xrom_test	simont	7933d 20h	/8051/tags/rel_2/
65	add oc8051_icache and oc8051_cache_ram	simont	7933d 20h	/8051/tags/rel_2/
64	signal es_int=1'b0	simont	7933d 20h	/8051/tags/rel_2/