URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 87

Rev	Log message	Author	Age	Path
87	add include oc8051_defines.v	simont	7879d 15h	/8051/tags/rel_2/
86	initial input	simont	7879d 15h	/8051/tags/rel_2/
85	prepare bugs	simont	7879d 15h	/8051/tags/rel_2/
84	remove wb_bus_mon	simont	7887d 14h	/8051/tags/rel_2/
83	replace some modules	simont	7887d 14h	/8051/tags/rel_2/
82	replace some modules	simont	7887d 14h	/8051/tags/rel_2/
81	initial import	simont	7887d 14h	/8051/tags/rel_2/
80	removing unused modules	simont	7887d 15h	/8051/tags/rel_2/
79	initial import	simont	7887d 15h	/8051/tags/rel_2/
78	alu with registered outputs	simont	7947d 14h	/8051/tags/rel_2/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7956d 11h	/8051/tags/rel_2/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7956d 11h	/8051/tags/rel_2/
75	initial import	simont	7956d 11h	/8051/tags/rel_2/
74	add module oc8051_wb_iinterface	simont	7964d 12h	/8051/tags/rel_2/
73	initial import	simont	7964d 12h	/8051/tags/rel_2/
72	fix bug in interface to external data ram	simont	7964d 14h	/8051/tags/rel_2/
71	add cache	simont	7968d 13h	/8051/tags/rel_2/
70	initial import	simont	7968d 13h	/8051/tags/rel_2/
69	add parameters	simont	7968d 15h	/8051/tags/rel_2/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7968d 15h	/8051/tags/rel_2/