URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 90

Rev	Log message	Author	Age	Path
90	change module name.	simont	7782d 23h	/8051/tags/rel_2/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7844d 02h	/8051/tags/rel_2/
88	fix bugs	simont	7849d 03h	/8051/tags/rel_2/
87	add include oc8051_defines.v	simont	7849d 03h	/8051/tags/rel_2/
86	initial input	simont	7849d 03h	/8051/tags/rel_2/
85	prepare bugs	simont	7849d 03h	/8051/tags/rel_2/
84	remove wb_bus_mon	simont	7857d 02h	/8051/tags/rel_2/
83	replace some modules	simont	7857d 02h	/8051/tags/rel_2/
82	replace some modules	simont	7857d 02h	/8051/tags/rel_2/
81	initial import	simont	7857d 02h	/8051/tags/rel_2/
80	removing unused modules	simont	7857d 02h	/8051/tags/rel_2/
79	initial import	simont	7857d 03h	/8051/tags/rel_2/
78	alu with registered outputs	simont	7917d 02h	/8051/tags/rel_2/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7925d 23h	/8051/tags/rel_2/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7925d 23h	/8051/tags/rel_2/
75	initial import	simont	7925d 23h	/8051/tags/rel_2/
74	add module oc8051_wb_iinterface	simont	7934d 00h	/8051/tags/rel_2/
73	initial import	simont	7934d 00h	/8051/tags/rel_2/
72	fix bug in interface to external data ram	simont	7934d 02h	/8051/tags/rel_2/
71	add cache	simont	7938d 01h	/8051/tags/rel_2/