URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] - Rev 103

Rev	Log message	Author	Age	Path
103	rename signals	simont	7846d 22h	/8051/tags/rel_2/bench/
97	initial inport	simont	7847d 01h	/8051/tags/rel_2/bench/
96	initial import	simont	7847d 01h	/8051/tags/rel_2/bench/
84	remove wb_bus_mon	simont	7925d 22h	/8051/tags/rel_2/bench/
74	add module oc8051_wb_iinterface	simont	8002d 20h	/8051/tags/rel_2/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	8006d 23h	/8051/tags/rel_2/bench/
59	add external rom	simont	8013d 18h	/8051/tags/rel_2/bench/
46	prepared header	simont	8030d 19h	/8051/tags/rel_2/bench/
37	added signals ack, stb and cyc	simont	8057d 22h	/8051/tags/rel_2/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	8078d 01h	/8051/tags/rel_2/bench/
2	Initial CVS import	simont	8093d 23h	/8051/tags/rel_2/bench/