URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5563d 05h	/8051/tags/rel_2/bench/
185		root	5619d 06h	/8051/tags/rel_2/bench/
180	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7698d 00h	/8051/tags/rel_2/bench/
170	removing unused files.	simont	7720d 04h	/8051/tags/rel_2/bench/
169	remove unused files.	simont	7720d 04h	/8051/tags/rel_2/bench/
167	add readmem for ea.	simont	7723d 10h	/8051/tags/rel_2/bench/
166	Change test monitor from ports to external data memory.	simont	7724d 03h	/8051/tags/rel_2/bench/
165	remove dumpvars.	simont	7724d 08h	/8051/tags/rel_2/bench/
164	initial inport.	simont	7724d 08h	/8051/tags/rel_2/bench/
163	initial inport	simont	7724d 08h	/8051/tags/rel_2/bench/
157	change data output.	simont	7724d 09h	/8051/tags/rel_2/bench/
156	add FREQ paremeter.	simont	7724d 09h	/8051/tags/rel_2/bench/
155	add aditional tests.	simont	7724d 09h	/8051/tags/rel_2/bench/
130	prepared programs for new timing.	simont	7765d 03h	/8051/tags/rel_2/bench/
129	updated...	simont	7765d 03h	/8051/tags/rel_2/bench/
125	update, add prescaler, rclk, tclk.	simont	7774d 11h	/8051/tags/rel_2/bench/
124	add support for external rom from xilinx ramb4	simont	7774d 11h	/8051/tags/rel_2/bench/
120	defines for pherypherals added	simont	7780d 08h	/8051/tags/rel_2/bench/
111	Remove instruction cache and wb_interface	simont	7787d 01h	/8051/tags/rel_2/bench/
103	rename signals	simont	7788d 05h	/8051/tags/rel_2/bench/