URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] - Rev 74

Rev	Log message	Author	Age	Path
74	add module oc8051_wb_iinterface	simont	7984d 10h	/8051/tags/rel_2/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7988d 14h	/8051/tags/rel_2/bench/
59	add external rom	simont	7995d 08h	/8051/tags/rel_2/bench/
46	prepared header	simont	8012d 10h	/8051/tags/rel_2/bench/
37	added signals ack, stb and cyc	simont	8039d 12h	/8051/tags/rel_2/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	8059d 16h	/8051/tags/rel_2/bench/
2	Initial CVS import	simont	8075d 14h	/8051/tags/rel_2/bench/