URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] - Rev 96

Rev	Log message	Author	Age	Path
96	initial import	simont	7757d 18h	/8051/tags/rel_2/bench/
84	remove wb_bus_mon	simont	7836d 15h	/8051/tags/rel_2/bench/
74	add module oc8051_wb_iinterface	simont	7913d 13h	/8051/tags/rel_2/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7917d 16h	/8051/tags/rel_2/bench/
59	add external rom	simont	7924d 10h	/8051/tags/rel_2/bench/
46	prepared header	simont	7941d 12h	/8051/tags/rel_2/bench/
37	added signals ack, stb and cyc	simont	7968d 14h	/8051/tags/rel_2/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	7988d 18h	/8051/tags/rel_2/bench/
2	Initial CVS import	simont	8004d 16h	/8051/tags/rel_2/bench/