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[/] [8051/] [tags/] [rel_2/] [bench/] [verilog/] - Rev 186

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Rev Log message Author Age Path
186 root 5551d 18h /8051/tags/rel_2/bench/verilog/
185 root 5607d 20h /8051/tags/rel_2/bench/verilog/
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7686d 13h /8051/tags/rel_2/bench/verilog/
167 add readmem for ea. simont 7711d 23h /8051/tags/rel_2/bench/verilog/
166 Change test monitor from ports to external data memory. simont 7712d 16h /8051/tags/rel_2/bench/verilog/
165 remove dumpvars. simont 7712d 21h /8051/tags/rel_2/bench/verilog/
157 change data output. simont 7712d 22h /8051/tags/rel_2/bench/verilog/
156 add FREQ paremeter. simont 7712d 22h /8051/tags/rel_2/bench/verilog/
125 update, add prescaler, rclk, tclk. simont 7763d 00h /8051/tags/rel_2/bench/verilog/
124 add support for external rom from xilinx ramb4 simont 7763d 00h /8051/tags/rel_2/bench/verilog/
120 defines for pherypherals added simont 7768d 21h /8051/tags/rel_2/bench/verilog/
111 Remove instruction cache and wb_interface simont 7775d 14h /8051/tags/rel_2/bench/verilog/
103 rename signals simont 7776d 19h /8051/tags/rel_2/bench/verilog/
97 initial inport simont 7776d 22h /8051/tags/rel_2/bench/verilog/
84 remove wb_bus_mon simont 7855d 19h /8051/tags/rel_2/bench/verilog/
74 add module oc8051_wb_iinterface simont 7932d 17h /8051/tags/rel_2/bench/verilog/
68 add instruction cache and DELAY parameters for external ram, rom simont 7936d 20h /8051/tags/rel_2/bench/verilog/
59 add external rom simont 7943d 15h /8051/tags/rel_2/bench/verilog/
46 prepared header simont 7960d 16h /8051/tags/rel_2/bench/verilog/
37 added signals ack, stb and cyc simont 7987d 19h /8051/tags/rel_2/bench/verilog/

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