URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] [verilog/] - Rev 166

Rev	Log message	Author	Age	Path
166	Change test monitor from ports to external data memory.	simont	7706d 22h	/8051/tags/rel_2/bench/verilog/
165	remove dumpvars.	simont	7707d 02h	/8051/tags/rel_2/bench/verilog/
157	change data output.	simont	7707d 04h	/8051/tags/rel_2/bench/verilog/
156	add FREQ paremeter.	simont	7707d 04h	/8051/tags/rel_2/bench/verilog/
125	update, add prescaler, rclk, tclk.	simont	7757d 05h	/8051/tags/rel_2/bench/verilog/
124	add support for external rom from xilinx ramb4	simont	7757d 05h	/8051/tags/rel_2/bench/verilog/
120	defines for pherypherals added	simont	7763d 03h	/8051/tags/rel_2/bench/verilog/
111	Remove instruction cache and wb_interface	simont	7769d 20h	/8051/tags/rel_2/bench/verilog/
103	rename signals	simont	7771d 00h	/8051/tags/rel_2/bench/verilog/
97	initial inport	simont	7771d 04h	/8051/tags/rel_2/bench/verilog/
84	remove wb_bus_mon	simont	7850d 01h	/8051/tags/rel_2/bench/verilog/
74	add module oc8051_wb_iinterface	simont	7926d 23h	/8051/tags/rel_2/bench/verilog/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7931d 02h	/8051/tags/rel_2/bench/verilog/
59	add external rom	simont	7937d 20h	/8051/tags/rel_2/bench/verilog/
46	prepared header	simont	7954d 22h	/8051/tags/rel_2/bench/verilog/
37	added signals ack, stb and cyc	simont	7982d 00h	/8051/tags/rel_2/bench/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	8002d 04h	/8051/tags/rel_2/bench/verilog/
2	Initial CVS import	simont	8018d 02h	/8051/tags/rel_2/bench/verilog/