URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] - Rev 116

Rev	Log message	Author	Age	Path
116	change sfr's interface.	simont	7772d 01h	/8051/tags/rel_2/rtl/
115	change uart to meet timing.	simont	7772d 03h	/8051/tags/rel_2/rtl/
114	remove t2mod register	simont	7775d 06h	/8051/tags/rel_2/rtl/
113	signal prsc_ow added.	simont	7775d 06h	/8051/tags/rel_2/rtl/
112	change timers to meet timing specifications (add divider with 12)	simont	7775d 06h	/8051/tags/rel_2/rtl/
110	change adr_i and adr_o length.	simont	7775d 21h	/8051/tags/rel_2/rtl/
109	add `include "oc8051_defines.v"	simont	7775d 21h	/8051/tags/rel_2/rtl/
108	fix some bugs, use oc8051_cache_ram.	simont	7775d 21h	/8051/tags/rel_2/rtl/
107	Include instruction cache.	simont	7775d 21h	/8051/tags/rel_2/rtl/
105	generic_dpram used	simont	7777d 00h	/8051/tags/rel_2/rtl/
104	use generic_dpram	simont	7777d 00h	/8051/tags/rel_2/rtl/
102	raname signals.	simont	7777d 01h	/8051/tags/rel_2/rtl/
95	updating...	simont	7777d 05h	/8051/tags/rel_2/rtl/
94	fix bug.	simont	7777d 05h	/8051/tags/rel_2/rtl/
93	OC8051_XILINX_RAM added	simont	7777d 05h	/8051/tags/rel_2/rtl/
92	initial inport	simont	7777d 05h	/8051/tags/rel_2/rtl/
90	change module name.	simont	7781d 23h	/8051/tags/rel_2/rtl/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7843d 02h	/8051/tags/rel_2/rtl/
88	fix bugs	simont	7848d 02h	/8051/tags/rel_2/rtl/
87	add include oc8051_defines.v	simont	7848d 03h	/8051/tags/rel_2/rtl/