URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] - Rev 137

Rev	Log message	Author	Age	Path
137	change to fit xrom.	simont	7756d 18h	/8051/tags/rel_2/rtl/
136	registering outputs.	simont	7756d 18h	/8051/tags/rel_2/rtl/
135	prepared start of receiving if ren is not active.	simont	7762d 17h	/8051/tags/rel_2/rtl/
134	fix bug in case execution of two data dependent instructions.	simont	7762d 17h	/8051/tags/rel_2/rtl/
133	fix bug in substraction.	simont	7762d 20h	/8051/tags/rel_2/rtl/
132	change branch instruction execution (reduse needed clock periods).	simont	7766d 11h	/8051/tags/rel_2/rtl/
128	chance idat_ir to 24 bit wide	simont	7775d 18h	/8051/tags/rel_2/rtl/
127	fix bug (cyc_o and stb_o)	simont	7775d 18h	/8051/tags/rel_2/rtl/
126	define OC8051_XILINX_RAMB added	simont	7775d 18h	/8051/tags/rel_2/rtl/
123	fiz bug iv pcs operation.	simont	7777d 14h	/8051/tags/rel_2/rtl/
122	deifne OC8051_ROM added	simont	7780d 18h	/8051/tags/rel_2/rtl/
121	Change pc add value from 23'h to 16'h	simont	7780d 18h	/8051/tags/rel_2/rtl/
120	defines for pherypherals added	simont	7781d 16h	/8051/tags/rel_2/rtl/
119	remove signal sbuf_txd [12:11]	simont	7781d 20h	/8051/tags/rel_2/rtl/
118	change wr_sft to 2 bit wire.	simont	7782d 12h	/8051/tags/rel_2/rtl/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7782d 13h	/8051/tags/rel_2/rtl/
116	change sfr's interface.	simont	7784d 14h	/8051/tags/rel_2/rtl/
115	change uart to meet timing.	simont	7784d 15h	/8051/tags/rel_2/rtl/
114	remove t2mod register	simont	7787d 18h	/8051/tags/rel_2/rtl/
113	signal prsc_ow added.	simont	7787d 18h	/8051/tags/rel_2/rtl/