URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] - Rev 89

Rev	Log message	Author	Age	Path
89	Replaced oc8051_ram by generic_dpram.	rherveille	7839d 23h	/8051/tags/rel_2/rtl/
88	fix bugs	simont	7844d 23h	/8051/tags/rel_2/rtl/
87	add include oc8051_defines.v	simont	7844d 23h	/8051/tags/rel_2/rtl/
82	replace some modules	simont	7852d 23h	/8051/tags/rel_2/rtl/
81	initial import	simont	7852d 23h	/8051/tags/rel_2/rtl/
80	removing unused modules	simont	7852d 23h	/8051/tags/rel_2/rtl/
78	alu with registered outputs	simont	7912d 23h	/8051/tags/rel_2/rtl/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7921d 20h	/8051/tags/rel_2/rtl/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7921d 20h	/8051/tags/rel_2/rtl/
75	initial import	simont	7921d 20h	/8051/tags/rel_2/rtl/
73	initial import	simont	7929d 20h	/8051/tags/rel_2/rtl/
72	fix bug in interface to external data ram	simont	7929d 22h	/8051/tags/rel_2/rtl/
67	add parameters for instruction cache	simont	7933d 23h	/8051/tags/rel_2/rtl/
62	fix bugs in instruction interface	simont	7934d 20h	/8051/tags/rel_2/rtl/
54	cahnge interface to instruction rom	simont	7940d 18h	/8051/tags/rel_2/rtl/
47	remove unused files	simont	7957d 19h	/8051/tags/rel_2/rtl/
46	prepared header	simont	7957d 19h	/8051/tags/rel_2/rtl/
45	prepared header	simont	7957d 20h	/8051/tags/rel_2/rtl/
44	prepared header	simont	7957d 20h	/8051/tags/rel_2/rtl/
41	remove unused files	simont	7957d 22h	/8051/tags/rel_2/rtl/