URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [sim/] - Rev 83

Rev	Log message	Author	Age	Path
83	replace some modules	simont	7836d 01h	/8051/tags/rel_2/sim/
82	replace some modules	simont	7836d 02h	/8051/tags/rel_2/sim/
69	add parameters	simont	7917d 02h	/8051/tags/rel_2/sim/
66	added xrom_test	simont	7917d 23h	/8051/tags/rel_2/sim/
65	add oc8051_icache and oc8051_cache_ram	simont	7917d 23h	/8051/tags/rel_2/sim/
64	signal es_int=1'b0	simont	7917d 23h	/8051/tags/rel_2/sim/
63	initial import	simont	7917d 23h	/8051/tags/rel_2/sim/
58	add external rom testing	simont	7923d 21h	/8051/tags/rel_2/sim/
57	add module oc8051_xrom	simont	7923d 21h	/8051/tags/rel_2/sim/
56	initial CVS input	simont	7923d 21h	/8051/tags/rel_2/sim/
55	added parameter DELAY	simont	7923d 21h	/8051/tags/rel_2/sim/
46	prepared header	simont	7940d 22h	/8051/tags/rel_2/sim/
43	remove unused files	simont	7941d 00h	/8051/tags/rel_2/sim/
42	* empty log message *	simont	7941d 00h	/8051/tags/rel_2/sim/
41	remove unused files	simont	7941d 00h	/8051/tags/rel_2/sim/
37	added signals ack, stb and cyc	simont	7968d 01h	/8051/tags/rel_2/sim/
19	combinatorial loop removed	simont	7981d 21h	/8051/tags/rel_2/sim/
18	rst signal added	simont	7985d 02h	/8051/tags/rel_2/sim/
4	Code repaired to satisfy the linter; testbech fails	markom	7988d 05h	/8051/tags/rel_2/sim/
2	Initial CVS import	simont	8004d 02h	/8051/tags/rel_2/sim/