URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] - Rev 145

Rev	Log message	Author	Age	Path
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7796d 23h	/8051/trunk/
144	chsnge comp.des to des1	simont	7796d 23h	/8051/trunk/
143	add wire sub_result, conect it to des_acc and des1.	simont	7796d 23h	/8051/trunk/
142	optimize state machine.	simont	7798d 00h	/8051/trunk/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7798d 02h	/8051/trunk/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7798d 02h	/8051/trunk/
139	add aditional alu destination to solve critical path.	simont	7798d 20h	/8051/trunk/
138	Change buffering to save one clock per instruction.	simont	7798d 20h	/8051/trunk/
137	change to fit xrom.	simont	7799d 01h	/8051/trunk/
136	registering outputs.	simont	7799d 01h	/8051/trunk/
135	prepared start of receiving if ren is not active.	simont	7805d 00h	/8051/trunk/
134	fix bug in case execution of two data dependent instructions.	simont	7805d 00h	/8051/trunk/
133	fix bug in substraction.	simont	7805d 03h	/8051/trunk/
132	change branch instruction execution (reduse needed clock periods).	simont	7808d 18h	/8051/trunk/
131	prepare programs for new timing.	simont	7808d 18h	/8051/trunk/
130	prepared programs for new timing.	simont	7808d 18h	/8051/trunk/
129	updated...	simont	7808d 18h	/8051/trunk/
128	chance idat_ir to 24 bit wide	simont	7818d 01h	/8051/trunk/
127	fix bug (cyc_o and stb_o)	simont	7818d 01h	/8051/trunk/
126	define OC8051_XILINX_RAMB added	simont	7818d 01h	/8051/trunk/