URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [bench/] - Rev 129

Rev	Log message	Author	Age	Path
129	updated...	simont	7747d 18h	/8051/trunk/bench/
125	update, add prescaler, rclk, tclk.	simont	7757d 02h	/8051/trunk/bench/
124	add support for external rom from xilinx ramb4	simont	7757d 02h	/8051/trunk/bench/
120	defines for pherypherals added	simont	7762d 23h	/8051/trunk/bench/
111	Remove instruction cache and wb_interface	simont	7769d 16h	/8051/trunk/bench/
103	rename signals	simont	7770d 20h	/8051/trunk/bench/
97	initial inport	simont	7771d 00h	/8051/trunk/bench/
96	initial import	simont	7771d 00h	/8051/trunk/bench/
84	remove wb_bus_mon	simont	7849d 21h	/8051/trunk/bench/
74	add module oc8051_wb_iinterface	simont	7926d 19h	/8051/trunk/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7930d 22h	/8051/trunk/bench/
59	add external rom	simont	7937d 17h	/8051/trunk/bench/
46	prepared header	simont	7954d 18h	/8051/trunk/bench/
37	added signals ack, stb and cyc	simont	7981d 21h	/8051/trunk/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	8002d 00h	/8051/trunk/bench/
2	Initial CVS import	simont	8017d 22h	/8051/trunk/bench/