URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [bench/] [verilog/] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5581d 19h	/8051/trunk/bench/verilog/
185		root	5637d 21h	/8051/trunk/bench/verilog/
184	initial inport.	simont	7703d 01h	/8051/trunk/bench/verilog/
167	add readmem for ea.	simont	7742d 00h	/8051/trunk/bench/verilog/
166	Change test monitor from ports to external data memory.	simont	7742d 17h	/8051/trunk/bench/verilog/
165	remove dumpvars.	simont	7742d 22h	/8051/trunk/bench/verilog/
157	change data output.	simont	7743d 00h	/8051/trunk/bench/verilog/
156	add FREQ paremeter.	simont	7743d 00h	/8051/trunk/bench/verilog/
125	update, add prescaler, rclk, tclk.	simont	7793d 01h	/8051/trunk/bench/verilog/
124	add support for external rom from xilinx ramb4	simont	7793d 01h	/8051/trunk/bench/verilog/
120	defines for pherypherals added	simont	7798d 22h	/8051/trunk/bench/verilog/
111	Remove instruction cache and wb_interface	simont	7805d 15h	/8051/trunk/bench/verilog/
103	rename signals	simont	7806d 20h	/8051/trunk/bench/verilog/
97	initial inport	simont	7806d 23h	/8051/trunk/bench/verilog/
84	remove wb_bus_mon	simont	7885d 20h	/8051/trunk/bench/verilog/
74	add module oc8051_wb_iinterface	simont	7962d 18h	/8051/trunk/bench/verilog/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7966d 21h	/8051/trunk/bench/verilog/
59	add external rom	simont	7973d 16h	/8051/trunk/bench/verilog/
46	prepared header	simont	7990d 17h	/8051/trunk/bench/verilog/
37	added signals ack, stb and cyc	simont	8017d 20h	/8051/trunk/bench/verilog/