URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 120

Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7763d 10h	/8051/trunk/rtl/
119	remove signal sbuf_txd [12:11]	simont	7763d 14h	/8051/trunk/rtl/
118	change wr_sft to 2 bit wire.	simont	7764d 07h	/8051/trunk/rtl/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7764d 07h	/8051/trunk/rtl/
116	change sfr's interface.	simont	7766d 08h	/8051/trunk/rtl/
115	change uart to meet timing.	simont	7766d 09h	/8051/trunk/rtl/
114	remove t2mod register	simont	7769d 12h	/8051/trunk/rtl/
113	signal prsc_ow added.	simont	7769d 12h	/8051/trunk/rtl/
112	change timers to meet timing specifications (add divider with 12)	simont	7769d 12h	/8051/trunk/rtl/
110	change adr_i and adr_o length.	simont	7770d 04h	/8051/trunk/rtl/
109	add `include "oc8051_defines.v"	simont	7770d 04h	/8051/trunk/rtl/
108	fix some bugs, use oc8051_cache_ram.	simont	7770d 04h	/8051/trunk/rtl/
107	Include instruction cache.	simont	7770d 04h	/8051/trunk/rtl/
105	generic_dpram used	simont	7771d 07h	/8051/trunk/rtl/
104	use generic_dpram	simont	7771d 07h	/8051/trunk/rtl/
102	raname signals.	simont	7771d 08h	/8051/trunk/rtl/
95	updating...	simont	7771d 11h	/8051/trunk/rtl/
94	fix bug.	simont	7771d 12h	/8051/trunk/rtl/
93	OC8051_XILINX_RAM added	simont	7771d 12h	/8051/trunk/rtl/
92	initial inport	simont	7771d 12h	/8051/trunk/rtl/