URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 139

Rev	Log message	Author	Age	Path
139	add aditional alu destination to solve critical path.	simont	7738d 03h	/8051/trunk/rtl/
138	Change buffering to save one clock per instruction.	simont	7738d 03h	/8051/trunk/rtl/
137	change to fit xrom.	simont	7738d 08h	/8051/trunk/rtl/
136	registering outputs.	simont	7738d 08h	/8051/trunk/rtl/
135	prepared start of receiving if ren is not active.	simont	7744d 07h	/8051/trunk/rtl/
134	fix bug in case execution of two data dependent instructions.	simont	7744d 07h	/8051/trunk/rtl/
133	fix bug in substraction.	simont	7744d 10h	/8051/trunk/rtl/
132	change branch instruction execution (reduse needed clock periods).	simont	7748d 01h	/8051/trunk/rtl/
128	chance idat_ir to 24 bit wide	simont	7757d 08h	/8051/trunk/rtl/
127	fix bug (cyc_o and stb_o)	simont	7757d 08h	/8051/trunk/rtl/
126	define OC8051_XILINX_RAMB added	simont	7757d 08h	/8051/trunk/rtl/
123	fiz bug iv pcs operation.	simont	7759d 04h	/8051/trunk/rtl/
122	deifne OC8051_ROM added	simont	7762d 08h	/8051/trunk/rtl/
121	Change pc add value from 23'h to 16'h	simont	7762d 08h	/8051/trunk/rtl/
120	defines for pherypherals added	simont	7763d 06h	/8051/trunk/rtl/
119	remove signal sbuf_txd [12:11]	simont	7763d 10h	/8051/trunk/rtl/
118	change wr_sft to 2 bit wire.	simont	7764d 02h	/8051/trunk/rtl/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7764d 03h	/8051/trunk/rtl/
116	change sfr's interface.	simont	7766d 04h	/8051/trunk/rtl/
115	change uart to meet timing.	simont	7766d 05h	/8051/trunk/rtl/