URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 151

Rev	Log message	Author	Age	Path
151	remove pc_r register.	simont	7680d 00h	/8051/trunk/rtl/
150	fix some bugs.	simont	7680d 00h	/8051/trunk/rtl/
149	pipelined acces to axternal instruction interface added.	simont	7680d 00h	/8051/trunk/rtl/
148	include "8051_defines" added.	simont	7680d 00h	/8051/trunk/rtl/
146	fix bug in movc intruction.	simont	7702d 00h	/8051/trunk/rtl/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7707d 04h	/8051/trunk/rtl/
144	chsnge comp.des to des1	simont	7707d 04h	/8051/trunk/rtl/
143	add wire sub_result, conect it to des_acc and des1.	simont	7707d 04h	/8051/trunk/rtl/
142	optimize state machine.	simont	7708d 06h	/8051/trunk/rtl/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7708d 07h	/8051/trunk/rtl/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7708d 07h	/8051/trunk/rtl/
139	add aditional alu destination to solve critical path.	simont	7709d 01h	/8051/trunk/rtl/
138	Change buffering to save one clock per instruction.	simont	7709d 01h	/8051/trunk/rtl/
137	change to fit xrom.	simont	7709d 06h	/8051/trunk/rtl/
136	registering outputs.	simont	7709d 06h	/8051/trunk/rtl/
135	prepared start of receiving if ren is not active.	simont	7715d 05h	/8051/trunk/rtl/
134	fix bug in case execution of two data dependent instructions.	simont	7715d 05h	/8051/trunk/rtl/
133	fix bug in substraction.	simont	7715d 08h	/8051/trunk/rtl/
132	change branch instruction execution (reduse needed clock periods).	simont	7719d 00h	/8051/trunk/rtl/
128	chance idat_ir to 24 bit wide	simont	7728d 07h	/8051/trunk/rtl/