URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 158

Rev	Log message	Author	Age	Path
158	fix bug.	simont	7837d 19h	/8051/trunk/rtl/
153	`ifdef added.	simont	7839d 13h	/8051/trunk/rtl/
152	sub_result output added.	simont	7839d 13h	/8051/trunk/rtl/
151	remove pc_r register.	simont	7839d 13h	/8051/trunk/rtl/
150	fix some bugs.	simont	7839d 13h	/8051/trunk/rtl/
149	pipelined acces to axternal instruction interface added.	simont	7839d 13h	/8051/trunk/rtl/
148	include "8051_defines" added.	simont	7839d 14h	/8051/trunk/rtl/
146	fix bug in movc intruction.	simont	7861d 14h	/8051/trunk/rtl/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7866d 18h	/8051/trunk/rtl/
144	chsnge comp.des to des1	simont	7866d 18h	/8051/trunk/rtl/
143	add wire sub_result, conect it to des_acc and des1.	simont	7866d 18h	/8051/trunk/rtl/
142	optimize state machine.	simont	7867d 19h	/8051/trunk/rtl/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7867d 21h	/8051/trunk/rtl/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7867d 21h	/8051/trunk/rtl/
139	add aditional alu destination to solve critical path.	simont	7868d 15h	/8051/trunk/rtl/
138	Change buffering to save one clock per instruction.	simont	7868d 15h	/8051/trunk/rtl/
137	change to fit xrom.	simont	7868d 20h	/8051/trunk/rtl/
136	registering outputs.	simont	7868d 20h	/8051/trunk/rtl/
135	prepared start of receiving if ren is not active.	simont	7874d 19h	/8051/trunk/rtl/
134	fix bug in case execution of two data dependent instructions.	simont	7874d 19h	/8051/trunk/rtl/