URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5511d 19h	/8051/trunk/rtl/
185		root	5567d 20h	/8051/trunk/rtl/
181	Simulation reports added.	simont	7646d 12h	/8051/trunk/rtl/
179	add /* synopsys xx_case */ to case statments.	simont	7646d 13h	/8051/trunk/rtl/
178	x replaced with 0.	simont	7646d 15h	/8051/trunk/rtl/
177	Fix bug in case of writing and reading from same address.	simont	7657d 19h	/8051/trunk/rtl/
175	initial inport.	simont	7657d 20h	/8051/trunk/rtl/
174	ram modules added.	simont	7657d 20h	/8051/trunk/rtl/
173	simualtion `ifdef added	simont	7657d 20h	/8051/trunk/rtl/
172	BIST signals added.	simont	7660d 20h	/8051/trunk/rtl/
171	fix bug in DA operation.	simont	7668d 17h	/8051/trunk/rtl/
158	fix bug.	simont	7672d 23h	/8051/trunk/rtl/
153	`ifdef added.	simont	7674d 17h	/8051/trunk/rtl/
152	sub_result output added.	simont	7674d 17h	/8051/trunk/rtl/
151	remove pc_r register.	simont	7674d 17h	/8051/trunk/rtl/
150	fix some bugs.	simont	7674d 17h	/8051/trunk/rtl/
149	pipelined acces to axternal instruction interface added.	simont	7674d 17h	/8051/trunk/rtl/
148	include "8051_defines" added.	simont	7674d 17h	/8051/trunk/rtl/
146	fix bug in movc intruction.	simont	7696d 18h	/8051/trunk/rtl/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7701d 21h	/8051/trunk/rtl/