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URL https://opencores.org/ocsvn/8051/8051/trunk

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[/] [8051/] [trunk/] [rtl/] - Rev 20

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Rev Log message Author Age Path
20 multiplier and divider changed so they complete in 4 cycles markom 7983d 09h /8051/trunk/rtl/
19 combinatorial loop removed simont 7984d 02h /8051/trunk/rtl/
17 fix some bugs simont 7987d 07h /8051/trunk/rtl/
16 inputs ram and op2 removed simont 7987d 07h /8051/trunk/rtl/
15 commbinatorial loop removed simont 7987d 07h /8051/trunk/rtl/
13 some bug fix simont 7988d 06h /8051/trunk/rtl/
12 des1_r in alu port list simont 7988d 06h /8051/trunk/rtl/
11 des2_r removed simont 7988d 06h /8051/trunk/rtl/
10 % replaced with ^ in uart; some minor improvements markom 7988d 12h /8051/trunk/rtl/
9 removed unused compare states markom 7990d 05h /8051/trunk/rtl/
8 some IDS optimizations markom 7990d 05h /8051/trunk/rtl/
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 7990d 06h /8051/trunk/rtl/
6 psw combinatorial loop removed markom 7990d 08h /8051/trunk/rtl/
5 more linter corrections; 2 tests still fail markom 7990d 08h /8051/trunk/rtl/
4 Code repaired to satisfy the linter; testbech fails markom 7990d 10h /8051/trunk/rtl/
2 Initial CVS import simont 8006d 08h /8051/trunk/rtl/

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