URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 78

Rev	Log message	Author	Age	Path
78	alu with registered outputs	simont	8005d 20h	/8051/trunk/rtl/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	8014d 17h	/8051/trunk/rtl/
76	add module oc8051_sfr, 256 bytes internal ram	simont	8014d 17h	/8051/trunk/rtl/
75	initial import	simont	8014d 17h	/8051/trunk/rtl/
73	initial import	simont	8022d 18h	/8051/trunk/rtl/
72	fix bug in interface to external data ram	simont	8022d 19h	/8051/trunk/rtl/
67	add parameters for instruction cache	simont	8026d 21h	/8051/trunk/rtl/
62	fix bugs in instruction interface	simont	8027d 17h	/8051/trunk/rtl/
54	cahnge interface to instruction rom	simont	8033d 15h	/8051/trunk/rtl/
47	remove unused files	simont	8050d 17h	/8051/trunk/rtl/
46	prepared header	simont	8050d 17h	/8051/trunk/rtl/
45	prepared header	simont	8050d 17h	/8051/trunk/rtl/
44	prepared header	simont	8050d 18h	/8051/trunk/rtl/
41	remove unused files	simont	8050d 19h	/8051/trunk/rtl/
40	added sigals for interacting with external ram	simont	8070d 21h	/8051/trunk/rtl/
38	fix some bugs	simont	8077d 19h	/8051/trunk/rtl/
37	added signals ack, stb and cyc	simont	8077d 19h	/8051/trunk/rtl/
36	fix bugs in mode 0	simont	8077d 19h	/8051/trunk/rtl/
32	overflow repaired	simont	8079d 00h	/8051/trunk/rtl/
31	fix some bugs	simont	8085d 16h	/8051/trunk/rtl/