URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 87

Rev	Log message	Author	Age	Path
87	add include oc8051_defines.v	simont	7842d 11h	/8051/trunk/rtl/
82	replace some modules	simont	7850d 11h	/8051/trunk/rtl/
81	initial import	simont	7850d 11h	/8051/trunk/rtl/
80	removing unused modules	simont	7850d 11h	/8051/trunk/rtl/
78	alu with registered outputs	simont	7910d 11h	/8051/trunk/rtl/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7919d 07h	/8051/trunk/rtl/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7919d 08h	/8051/trunk/rtl/
75	initial import	simont	7919d 08h	/8051/trunk/rtl/
73	initial import	simont	7927d 08h	/8051/trunk/rtl/
72	fix bug in interface to external data ram	simont	7927d 10h	/8051/trunk/rtl/
67	add parameters for instruction cache	simont	7931d 11h	/8051/trunk/rtl/
62	fix bugs in instruction interface	simont	7932d 08h	/8051/trunk/rtl/
54	cahnge interface to instruction rom	simont	7938d 06h	/8051/trunk/rtl/
47	remove unused files	simont	7955d 07h	/8051/trunk/rtl/
46	prepared header	simont	7955d 07h	/8051/trunk/rtl/
45	prepared header	simont	7955d 08h	/8051/trunk/rtl/
44	prepared header	simont	7955d 08h	/8051/trunk/rtl/
41	remove unused files	simont	7955d 10h	/8051/trunk/rtl/
40	added sigals for interacting with external ram	simont	7975d 11h	/8051/trunk/rtl/
38	fix some bugs	simont	7982d 10h	/8051/trunk/rtl/