URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 92

Rev	Log message	Author	Age	Path
92	initial inport	simont	7848d 07h	/8051/trunk/rtl/
90	change module name.	simont	7853d 00h	/8051/trunk/rtl/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7914d 03h	/8051/trunk/rtl/
88	fix bugs	simont	7919d 04h	/8051/trunk/rtl/
87	add include oc8051_defines.v	simont	7919d 04h	/8051/trunk/rtl/
82	replace some modules	simont	7927d 04h	/8051/trunk/rtl/
81	initial import	simont	7927d 04h	/8051/trunk/rtl/
80	removing unused modules	simont	7927d 04h	/8051/trunk/rtl/
78	alu with registered outputs	simont	7987d 04h	/8051/trunk/rtl/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7996d 00h	/8051/trunk/rtl/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7996d 00h	/8051/trunk/rtl/
75	initial import	simont	7996d 00h	/8051/trunk/rtl/
73	initial import	simont	8004d 01h	/8051/trunk/rtl/
72	fix bug in interface to external data ram	simont	8004d 03h	/8051/trunk/rtl/
67	add parameters for instruction cache	simont	8008d 04h	/8051/trunk/rtl/
62	fix bugs in instruction interface	simont	8009d 01h	/8051/trunk/rtl/
54	cahnge interface to instruction rom	simont	8014d 23h	/8051/trunk/rtl/
47	remove unused files	simont	8032d 00h	/8051/trunk/rtl/
46	prepared header	simont	8032d 00h	/8051/trunk/rtl/
45	prepared header	simont	8032d 00h	/8051/trunk/rtl/