OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 146

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
146 fix bug in movc intruction. simont 7715d 20h /8051/trunk/rtl/verilog/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7721d 00h /8051/trunk/rtl/verilog/
144 chsnge comp.des to des1 simont 7721d 00h /8051/trunk/rtl/verilog/
143 add wire sub_result, conect it to des_acc and des1. simont 7721d 00h /8051/trunk/rtl/verilog/
142 optimize state machine. simont 7722d 01h /8051/trunk/rtl/verilog/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7722d 03h /8051/trunk/rtl/verilog/
140 cahnge assigment to pc_wait (remove istb_o) simont 7722d 03h /8051/trunk/rtl/verilog/
139 add aditional alu destination to solve critical path. simont 7722d 21h /8051/trunk/rtl/verilog/
138 Change buffering to save one clock per instruction. simont 7722d 21h /8051/trunk/rtl/verilog/
137 change to fit xrom. simont 7723d 02h /8051/trunk/rtl/verilog/
136 registering outputs. simont 7723d 02h /8051/trunk/rtl/verilog/
135 prepared start of receiving if ren is not active. simont 7729d 01h /8051/trunk/rtl/verilog/
134 fix bug in case execution of two data dependent instructions. simont 7729d 01h /8051/trunk/rtl/verilog/
133 fix bug in substraction. simont 7729d 04h /8051/trunk/rtl/verilog/
132 change branch instruction execution (reduse needed clock periods). simont 7732d 19h /8051/trunk/rtl/verilog/
128 chance idat_ir to 24 bit wide simont 7742d 02h /8051/trunk/rtl/verilog/
127 fix bug (cyc_o and stb_o) simont 7742d 02h /8051/trunk/rtl/verilog/
126 define OC8051_XILINX_RAMB added simont 7742d 02h /8051/trunk/rtl/verilog/
123 fiz bug iv pcs operation. simont 7743d 22h /8051/trunk/rtl/verilog/
122 deifne OC8051_ROM added simont 7747d 02h /8051/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.